GetCPUInfo method
Programmed by Héctor A. Medina
Syntax
Invoke GetCPUInfo, lpCPUInfo
Function
Executes the CPUID instruction (not available in all processors) and returns information about the CPU.
Parameters
lpCPUInfo
Address of a CPUINFO structure (Easy Code defined).
Return value
Eax returns TRUE if sucessful, or FALSE if not.
If successful, the CPUINFO
structure
will have been filled with various CPU information. This structure is
defined as follows:
CPUINFO Struct
Description DB 32 Dup 0 ; CPU description ('GenuineIntel', 'AuthenticAMD', etc.)
Stepping DD 0 ; Stepping ID
Family DD 0 ; Family (3 = 386, 4 = 486, 5 = Pentium, 6 = Pentium Pro)
Model DD 0 ; Model
CPUType DD 0 ; Reserved
ModelID DD 0 ; See 'REMARKS'
FeaturesID DD 0 ; See 'REMARKS'
ExFeaturesID DD 0 ; See 'REMARKS'
EndS
REMARKS: The CPUID
instruction
sets the Eax,
Ecx
and Edx
registers with
various information about the CPU. Although some of the information in
the Eax
register is already detailed in the Stepping,
Family, Model and CPUType
members
of the structure, the whole value is also stored in the ModelID
member. On the other hand, the
FeaturesID member stores the value set by CPUID in the Edx
register, while the ExFeaturesID member stores the
value
set by CPUID
in the Ecx
register (remember that Ecx
and Edx
are saved by the GetCPUInfo
method). These
values refer to compability flags and have the following
meaning:
FeaturesID:
Bit 0 | FPU on Chip |
Bit 1 | Virtual Mode Extention present |
Bit 2 | Debbuging Extentions |
Bit 3 | CPU support 4MB size pages |
Bit 4 | TSC present (See RDTSC command) |
Bit 5 | CPU have Pentium Compatible MSRs |
Bit 6 | Physical Address Extension (Intel), Support PTE (Cyrix) |
Bit 7 | Machine Check exception |
Bit 8 | Support CMPXCHG8B instruction |
Bit 9 | Local APIC on Chip (Intel), Page Global Extension (K5) |
Bit 10 | Reserved |
Bit 11 | Fast System Call feature (Pentium Pro) |
Bit 12 | CPU support Memory Type Range Register (MTRR) |
Bit 13 | Page Global Feature support |
Bit 14 | Machine Check Architecture |
Bit 15 | CPU support CMOV instruction |
Bit 16 | Page Attribute Table |
Bit 17 | CPU support 4MB Pages for access memory higher that 2GB |
Bit 18 | CPU Support Processor Serial Number |
Bit 19-22 | Reserved |
Bit 23 | CPU support IA MMX |
Bit 24 | CPU Support Fast Save/Restore (IA MMX-2) |
Bit 25 | Streaming SIMD Extension (IA MMX-2) |
Bit 26-31 | Reserved and set to 0s now |
ExFeaturesID:
Bit 0 | SSE3 - SSE3 Extensions |
Bit 1-2 | Reserved |
Bit 3 | MONITOR - MONITOR/MWAIT |
Bit 4 | DS-CPL - CPL Qualified Debug Store |
Bit 5 | VMX - Virtual Machine Technology |
Bit 6 | Reserved |
Bit 7 | EST - Enhanced Intel SpeedStep® Technology |
Bit 8 | TM2 - Thermal Monitor 2 |
Bit 9 | SSSE3 - SSSE3 Extensions |
Bit 10 | CNXT-ID - L1 Context ID |
Bit 11-12 | Reserved |
Bit 13 | CMPXCHG16B |
Bit 14 | xTPR Update Control |
Bit 15 | PDCM — Perf/Debug Capability MSR |
Bit 16-18 | Reserved |
Bit 19 | SSE4.1 |
Bit 20 | SSE4.2 |
Bit 21 | Reserved |
Bit 22 | Reserved |
Bit 23 | POPCNT |
Bit 24-31 | Reserved |